The present invention relates to a serial data interface circuit and, more particularly, to a serial data receiving circuit acceptable to a plurality of data receiving modes.
Serial data transfer is widely employed as a means for transferring data among a plurality of units. For example, a microcomputer as a data processing apparatus incorporates a serial data interface circuit to serially transfer processed data to a peripheral unit and/or to serially receive data to be processed from the peripheral unit. The data received serially is converted into parallel data which is subjected to a predetermined processing operation. The resultant data may be returned to the peripheral unit by the serial transfer.
From the view point of wide application, it is advantageous to design the bit length of serial-transferred data to be changeable. For instance, it is desirable to couple a 16-bit data processing apparatus with not only a 16-bit peripheral unit but a 8-bit peripheral unit. Further, the bit order of the serial-transferred data is desired to be changeable. This is because some peripheral units transfer data serially from the most significant bit (MSB) thereof and some other peripheral units transfer serial data from the least significant bit (LSB) thereof. The serial data receiving circuit is thus desired to deal with the following four receiving modes (1)-(4):
(1) The circuit receives data having bit length equal to the longest bit length allowed in one serial transfer and converts it into parallel data;
(2) The circuit receives data having bit length less than the longest bit length, converts it into parallel data and outputs only valid bit data;
(3) The circuit receives data having bit length equal to the longest bit length, converts it into parallel data and outputs the parallel data with reversing the bit order thereof; and
(4) The circuit receives data having bit length less than the longest bit length, converts it into parallel data and outputs only valid bit data with reversing the bit order thereof.